CURIN is Organizing a Workshop on Analog and Digital IC Design using Cadence Tools on 20-21 Dec 2014. The aim of this workshop is to provide hands-on experience on the state-of-the-art Cadence EDA tools for VLSI Design. The participants will have an exposure to the Circuit Design & Simulation, Layout, Physical Verification (DRC, LVS), and Extraction. The workshop includes practice sessions on the Cadence design and simulation tools (Encounter, RTL Compiler, Virtuoso, Spectre, Assura and Incisive). Workshop Topics · Introduction to Cadence and its various tools. · Basics of mixed signal design using Cadence Virtuoso. · Introduction to Physical Verification, DRC/LVS by Assura. · Implementation of NC Launch and RTL Compiler for Digital Circuit using Verilog. · Extraction of RC Components and Generation of GDSII file. Who can attend ? UG students working in area of VLSI design Researchers (Masters, Doctoral students and Fellows) with Thesis in VLSI Academicians for enhancing skills in delivering VLSI Labs at Institute/University Design Engineers from Industry For Registration, please contact Mr. Vishal Mehta Assistant Professor-Research CURIN, Chitkara University Rajpura, Punjab Phone: +91-9888836451 Email id: [email protected]
Posted on: Wed, 17 Dec 2014 10:31:54 +0000
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