Cpu Miner cpuminer is a simple client program that performs Pooled Mining or solo mining. The program receives proposed block data from the server, for which it tries to guess a nonce value that will result in a valid block. If a block hash with at least 32 consecutive zero bits is found, the block data containing the guessed nonce value is sent back to the server. If used in Pooled Mining mode, this block is called a share because the server is supposed to credit the registered users account, according to the number of shares that user has contributed, and eventually transfer an amount of bitcoins to the registered users address. Communication with the server is done using HTTP POST requests on port 8332 by default, containing JSON-encoded data. For pooled mining, users are required to register on such servers (so as to give their Bitcoin address) and HTTP username:password authentication is required. For solo mining, the username/password is set in bitcoin.conf. The calculations are performed by multiple concurrent threads, so as to take advantage of the capabilities of computers with multiple CPU cores. Contents • 1 Algorithms • 2 Succession • 3 See Also • 4 External Links Algorithms SHA256 hashes can be calculated in many ways by cpu-miner. Depending on the hardware that is used, one of the following supported algorithms will perform best: • c: Linux kernel implementation of SHA256 (supported on all platforms, including Windows) . • 4way: 128-bit SSE2 optimizations which are already available as a compile-time option on the classic Bitcoin client. • via: Implementation of the Padlock encryption optimizations on VIA CPUs. • cryptopp: C/C++ Implementation from the Crypto++ library. • cryptopp_asm32: 32-bit assembly implementation from the Crypto++ library. • sse2_64: Port of ufasofts SSE2 implementation (only supported on 64-bit Linux) Succession CPU Miner has largely been superceded by Con Kolivass cgminer fork (with GPU support) and Luke-Jrs BFGMiner fork (with FPGA support). See Also • Pooled mining External Links • Github repository with cpuminer code • Forum thread with announcement and discussion • Con Kolivass cgminer forum announcement and discussion BTCMiner BTCMiner - Bitcoin Miner for ZTEX FPGA boards BTCMiner is an Open Source Bitcoin Miner for ZTEX USB-FPGA Modules 1.15. These FPGA Boards contain an USB interface which is used for communication and programming (i.e. no JTAG programmer is required) and allows to build low cost FPGA clusters using standard components like USB hubs. The software runs on Linux and Windows. Features • Supported FPGA Boards: • Spartan 6 USB-FPGA Module 1.15b with one XC6SLX75: 90 MH/s @ 5.0W (typical) • Spartan 6 USB-FPGA Module 1.15d with one XC6SLX150: 215 MH/s @ 9.8W (typical) • Spartan 6 USB-FPGA Module 1.15x with one XC6SLX150: 215 MH/s @ 9.8W (typical) • Spartan 6 USB-FPGA Module 1.15y with four XC6SLX150: 860 MH/s @ 39W (typical) • Dynamic frequency scaling based on error measurement, i.e. BTCMiner automatically chooses the frequency with the highest rate of valid hashes. • Cluster mode with hot-plugging allows to run large amounts of FPGA Boards • Ready-to-use Bitstream, i.e. no Xilinx Software or License required Usage All files required are packed into a single jar archive which can be downloaded from the download section of the BTCMiner homepage and runs under Linux and Windows. Windows users need to install the libusb driver from the ZTEX SDK. A detailed description of the usage can be found at the BTCMiner homepage. Open Source FPGA Bitcoin Miner (Redirected from Open Source FGPA Bitcoin Miner) A miner that makes use of a compatible FPGA Board. The miner works either in a mining pool or solo. This is the first open source FPGA Bitcoin miner. It was released on May 20, 2011[1]. Contents • 1 Software needed • 2 Compiling o 2.1 Altera o 2.2 Changing the clock speed • 3 Programming the FPGA o 3.1 Altera o 3.2 Using urjtag • 4 Mining o 4.1 Altera • 5 See Also • 6 External Links • 7 References Software needed Currently programming and running the FPGAminer code requires Quartus II for Altera devices and Xilinx ISE Webpack for Xilinx devices. Quartus is 32bit only. The free ISE Webpack does not work on devices larger then Spartan6 LX75. Compiling Altera The compile the code on an different Altera device then DE2-115, you need to set the Device to be the correct one. Find the correct fpga package number and add it, for the DE0-Nano this is EP4CE22F17C6. Be sure to select the correct one, because the hardware effects the location of your pins, which you will need in the clock pin step. To get the provided code to compile on a smaller device, you need to set CONFIG_LOOP_LOG2 to a value between 0-5. Higher values shrink the size in so that 4 does approx. 12000 LUTs large program, while 0 is around 90000 LUTs. CONFIG_LOOP_LOG2 is set in the file fpgaminer.qsf. The fpgaminer_top.v file also has a similar setting, but it is an ifdef/it does not get set from there if the setting exists in the qsf. To make the code compile properly on an different device (not a DE2-115), you need to set the osc_clk pin to the clock pin of your device. This can be read from the device manual! On an DE0-Nano this pin is PIN_R8. This pin location varies between devices and you must look it up in your device manual. To set the pin location, open the assignment editor add new osc_clk and set its location to the pin specified in your manual, ie. for DE0-nano this is R8. For the DE2-115 this is PIN_Y2. Changing the clock speed NOTE: You can fry your FPGA doing this! Edit main_pll.v and find the line: altpll_component.clk0_multiply_by = 5, The way the Mhz is calculated is 50Mhz*multply_by/divide_by. Setting of 10 with default clk0_divide_by gives Mhz of 100, 8 is 80Mhz. Compile the code. Watch for critical warnings from synthesis. Run Powerplay power analyzer tool and set it with the cooling system you have. If there are no errors, you may at your own risk program the FPGA with the higher Mhz bitfile. Programming the FPGA On linux you need to set udev rules for the UsbBlaster cable to work. Under arch these are under /etc/udev/rules.d/ add a file called 51-altera.rules. #####altera usb blaster BUS==usb, SYSFS{idVendor}==09fb, SYSFS{idProduct}==6001, MODE=0666, SYMLINK+=usbblaster Altera Copy the .sof file from the quartus output directory under your project directory to the scripts/program directory and execute /quartus_stp -t program.tcl, then select the device you want programmed and then the sof file you moved to the directory. Using urjtag (unconfirmed to work, lights blink though) $ sudo jtag > cable UsbBlaster > bsdl path /usr/share/urjtag/bsdl/EP4CE22F17C6_pre.bsd > detect > svf fpgaminer.svf Mining Altera The new mining and programming scripts find the connected devices now. Just edit the config.tcl to have your details. See Also • Mining Pool External Links • Open-Source-FPGA-Bitcoin-Miner project on GitHub References 1. ↑ Official Open Source FPGA Bitcoin Miner (Just Released!) Remote miner An open source Bitcoin pooled mining server created by puddinpop. The clients connect through a JSON-based protocol with the RPC Miner pooled mining clients created by puddinpop. The distribution includes: • remoteminer server for CPU • remoteminer server for 4Way • remoteminer server for ATI OpenCL GPUs • remoteminer server for NVidia CUDA GPUs See Also • puddinpopps RPC Miner client • Pooled Mining • Why a GPU mines faster than a CPU External Links • bitcoin-remote-rpc server and client source • bitcoin-remote server binaries for Windows • Project Thread Open Source FPGA Bitcoin Miner (Redirected from Open Source FGPA Bitcoin Miner) A miner that makes use of a compatible FPGA Board. The miner works either in a mining pool or solo. This is the first open source FPGA Bitcoin miner. It was released on May 20, 2011[1]. Contents • 1 Software needed • 2 Compiling o 2.1 Altera o 2.2 Changing the clock speed • 3 Programming the FPGA o 3.1 Altera o 3.2 Using urjtag • 4 Mining o 4.1 Altera • 5 See Also • 6 External Links • 7 References Software needed Currently programming and running the FPGAminer code requires Quartus II for Altera devices and Xilinx ISE Webpack for Xilinx devices. Quartus is 32bit only. The free ISE Webpack does not work on devices larger then Spartan6 LX75. Compiling Altera The compile the code on an different Altera device then DE2-115, you need to set the Device to be the correct one. Find the correct fpga package number and add it, for the DE0-Nano this is EP4CE22F17C6. Be sure to select the correct one, because the hardware effects the location of your pins, which you will need in the clock pin step. To get the provided code to compile on a smaller device, you need to set CONFIG_LOOP_LOG2 to a value between 0-5. Higher values shrink the size in so that 4 does approx. 12000 LUTs large program, while 0 is around 90000 LUTs. CONFIG_LOOP_LOG2 is set in the file fpgaminer.qsf. The fpgaminer_top.v file also has a similar setting, but it is an ifdef/it does not get set from there if the setting exists in the qsf. To make the code compile properly on an different device (not a DE2-115), you need to set the osc_clk pin to the clock pin of your device. This can be read from the device manual! On an DE0-Nano this pin is PIN_R8. This pin location varies between devices and you must look it up in your device manual. To set the pin location, open the assignment editor add new osc_clk and set its location to the pin specified in your manual, ie. for DE0-nano this is R8. For the DE2-115 this is PIN_Y2. Changing the clock speed NOTE: You can fry your FPGA doing this! Edit main_pll.v and find the line: altpll_component.clk0_multiply_by = 5, The way the Mhz is calculated is 50Mhz*multply_by/divide_by. Setting of 10 with default clk0_divide_by gives Mhz of 100, 8 is 80Mhz. Compile the code. Watch for critical warnings from synthesis. Run Powerplay power analyzer tool and set it with the cooling system you have. If there are no errors, you may at your own risk program the FPGA with the higher Mhz bitfile. Programming the FPGA On linux you need to set udev rules for the UsbBlaster cable to work. Under arch these are under /etc/udev/rules.d/ add a file called 51-altera.rules. #####altera usb blaster BUS==usb, SYSFS{idVendor}==09fb, SYSFS{idProduct}==6001, MODE=0666, SYMLINK+=usbblaster Altera Copy the .sof file from the quartus output directory under your project directory to the scripts/program directory and execute /quartus_stp -t program.tcl, then select the device you want programmed and then the sof file you moved to the directory. Using urjtag (unconfirmed to work, lights blink though) $ sudo jtag > cable UsbBlaster > bsdl path /usr/share/urjtag/bsdl/EP4CE22F17C6_pre.bsd > detect > svf fpgaminer.svf Mining Altera The new mining and programming scripts find the connected devices now. Just edit the config.tcl to have your details. See Also • Mining Pool External Links • Open-Source-FPGA-Bitcoin-Miner project on GitHub References 1. ↑ Official Open Source FPGA Bitcoin Miner (Just Released!)
Posted on: Mon, 08 Dec 2014 07:17:34 +0000
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