Disadvantages Synchronous Reset: >The problem in this topology is with reset assertion. If the reset signal is not long enough to be captured at active clock edge (or the clock may be slow to capture the reset signal), it will result in failure of assertion. In such case the design needs a pulse stretcher to guarantee that a reset pulse is wide enough to be present during the active clock edge. >Another problem with synchronous resets is that the logic synthesis cannot easily distinguish the reset signal from any other data signal. So proper care has to be taken with logic synthesis, else the reset signal may take the fastest path to the flip-flop input there by making worst case timing hard to meet. >In some power saving designs the clocked is gated. In such designed only asynchronous reset will work. >Faster designs that are demanding low data path timing, can not afford to have extra gates and additional net delays in the data path due to logic inserted to handle synchronous resets. #Disadvantages #Synchronous_Reset Next Update What is Asynchronous Reset ???(Follow us) : goo.gl/fA8Fx9
Posted on: Sat, 02 Nov 2013 16:30:00 +0000
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