Senior Research Engineer (EDA & PDK) – Up to $6000 – West (Ref: CS0403) Position : Senior Research Engineer (EDA & PDK) Location : Science Park Working hours : 5 Days / Office Hours Salary : Up to $6000 Duration : Perm Main Responsibilities: - Set up EDA (Electronic Design Automation) / PDK (Process Design Kit) platforms - Support automation tools/utilities for all aspects of tape-out operations - Set up the framework for design automation with commercial EDA tools e.g. Cadence, Mentor Graphics. - Work closely with end users (e.g., internal designer and also external, such as MPW users) to understand design specifications and requirement - Work with program’s EDA responsible staffs in the development of automation tools/utilities for a given design environment. - Work closely with Integrated Circuits & System (ICS) department to ensure accuracy and completeness of the final product; - Work with various program groups in long term for the establishment of specific PDKs, and participate in crossfunctional/ fields team collaboration; - Assist each program to: -Do analysis, design, developing, testing, modeling, towards the establishment of specific PDK, device library, and also maintaining, upgrading with device library, -Ensure standardization and Centralization of the design environment - Develop information sharing mechanisms and participating in cross-functional team collaboration - Identify user EDA needs and propose solutions Requirements: - Candidate must possess at least a Diploma, Advanced/Higher/Graduate Diploma, Bachelors Degree, Post Graduate Diploma, Professional Degree, Masters Degree in Electrical/Computer Engineering/ VLSI or equivalent - Minimum 5 years of experience in PDK set-up, CAD methodology, EDA tool development, CAD flow development; Background in CAD/EDA support, particular with Knowledge of Design tool Debug, Integration of various commercial tools, and Design Flow Improvements. - Candidate must possess: - Strong expertise in Cadence - Mentor Graphics Design and Verification tools, e.g., Virtuoso layout, Calibre for layout verification (DRC/LVS/PEX) - iPDK (Analog and Digital Design and Verification tools);Complex P-Cell programming (SKILL/MCell) & CDF/Symbol; Database knowledge and Modeling; Design Rule Deck, LVS, PEX Coding - Knowledge of semiconductor device Physics and Front-Back-Ends Processing - Shell or other language is required for task automation; - Lab measurements on PCM and interpreting results from automated testing from such structures - Good knowledge on EDA IC Design flows, tools, vendors and flows, tools related to Integrated circuit design, including Cadence, Mentor, Synopsys and data management - Strong analytical capability to understand business issues and analyze user requirements - Experience in Solid Scripting Skills in Perl, Python, TCL, SKILL, LISP, C or Shell and development of CAD utilities will be an added advantage - Only Singaporeans If you possess the above qualities, take the next step today to launch your new career! How to apply: Send in your comprehensive resume with your qualifications, work experiences, current & expected salaries, earliest starting date and contact details to in MS WORD FORMAT to [email protected] or feel free to call Claire at 6679 5678 for more information. Likes us on FB for career tips and more job opportunities: https://facebook/search.personnel *We dont charge our candidate any referral fee. Licence no. 13C6684 EA Personnel ID: R1435028
Posted on: Wed, 05 Mar 2014 06:09:24 +0000
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