VLSI Projects|VHDL Projects|MATLAB Projects: 3-D Lifting-based Discrete Wavelet Transform 4 BIT SFQ Multiplier 8 Bit PICCO Processor A Framework for Correction of Multi-Bit Soft Errors A Processor-In-Memory Architecture For Multimedia Compression Adiabatic Technique For Energy Efficient Logic Circuits Design Advanced Encryption System to Improvise System Speed AMBA-Advanced High Performance Bus IP Block ASIC Design Of Complex Multiplier Asynchronous Transfer Mode Knockout Switch Automatic Road Extraction Using High Resolution Satellite Images Behavioral Synthesis of Asynchronous Circuits Building An AMBA AHB Compliant Memory Controller Carry Tree Adder Cordic Processor for Complex DPLL Custom Floating-Point Unit Generation Cyclic Redundancy Checker Generator Design of Data Encryption Standard (DES) for Data Encryption DDR3 Based Lookup Circuit for High Performance Network Processing Design and Implementation of Efficient Systolic Array Architecture Design and Implementation of High Speed DDR SDRAM Controller Design And Synthesis Of Programmable Logic Block Design Of Reversible Finite Field Arithmetic Design of 16 BIT QPSK Design of 16 Point Radix-4 FFT Algorithm Design Of 32 Bit RISC Processor Design of 64-Bit QAM Design of A Bus Bridge Between AHB and OCP Design of Control Area Network Protocol Design of Finite Impulse Response Filter Design of JPEG Compression Standard Design of On-Chip Bus with OCP Interface Design of Phelix Algorithm Design Of Radix-2 Butterfly processor to prevent Overflow in The Arithmetic Designing Efficient Online Testable Reversible Adders Detecting Background Setting For Dynamic Scene Digital Base Band Processor for UWB Transceiver Direct Digital Frequency Synthesizer Dual Data Rate SDRAM Controller Dual Elevator Controller Dual Stack Method Efficient FPGA Implementation Of Convolution Exploitation of Narrow-Width Values Fault Secure Encoder Floating Point Multiplier Floating Point Vector Coprocessor FPGA-Based Architecture For Linear And Morphological Image Filtering General Linear Feedback Shift Register High Performance Complex Number Multiplier Using Booth-Wallace Algorithm High Throughput DA-Based DCT With High Accuracy High-Accuracy Fixed-Width Modified Booth Multipliers High-Speed Low-Power Viterbi Decoder Design For TCM Decoders Implementation Of Discrete Wavelet Transform Implementation of FFT/IFFT Blocks for OFDM Implementation Of Guessing Game Implementation of Hamming Code JPEG Image Compression LFSR Based Test Generator Synthesis Lightweight High-Performance Fault Detection Scheme Lossless Implementation Of Daubechies 8-Tap Wavelet Transform Low Power ALU Design By Ancient Mathematics Low Power Flip-Flop Using Cmos Deep Submicron Technology Low Power Hardware Architecture for VBSME using Pixel Truncation Low-Complexity Sequential Searcher For Robust Symbol Synchronization In OFDM Systems Low-Power And Area-Efficient Carry Select Adder Module To Implement I2C Interface Multilayer AHB Bus Matrix Multiplication Acceleration Through Twin Precision New Adaptive Weight Algorithm For Salt And Pepper Noise Removal Novel Area-Efficient FPGA Architectures OFDM Transmitter and Receiver Using FPGA Operation Improvement of Indoor Robot Parallel Prefix Adders Using FPGAS Performance Analysis of Integer Wavelet Transform For Image Compression Pipeline VLSI Architecture Power Management Of MIMO Network Interfaces On Mobile Systems Programmable Logic Block With Mixed LUT and MACROGATE Quadrature Phase Shifting key Modulator Module Design Of Parallel Multiplier Based On RADIX-2 Modified Booth Algorithm Rail-Passenger Information System Reconfigurable Coprocessor for Redundant Radix-4 Arithmetic REED SOLMEN ENCODER Register For Phase Difference Based Logic Reliable and Cost Effective Anti-collision Technique For RFID UHF Tag Removal Of High Density Salt And Pepper Noise Rotation-Based Bist With Self-Feedback Seal Encryption On FPGA, GPU AND Multi-Core Processors Self-Immunity Technique to Improve Register File Integrity against Soft Errors Shift-Register-Based Data Transposition Short Range MIMO Communications Soft-Error Tolerance and Mitigation Spurious-Power Suppression Technique for Multimedia/DSP Applications Task Migration In Mesh NOCS Traffic Light Controller Triple Des Algoritm Turbo Encoder For LTE Process Universal Asynchronous Receiver Transmitter Very Fast and Low Power Carry Select Adder Circuit Viterbi Decoder for High Speed Applications VLSI Progressive Coding for Wavelet-based Image Compression
Posted on: Mon, 12 Aug 2013 01:48:57 +0000